System Pll - Freescale Semiconductor MPC850 User Manual

32 kHz: R1=20MΩ, R2=330kΩ, C1=20pF, C2=20pF
4 MHz: R1=10MΩ, R2=1kΩ, C1=47 pF, C2=56 pF

14.2.2 System PLL

The programmable phase-locked loop, called the system phase-locked loop (SPLL) in the
MPC850, generates the overall system operating frequency in integer multiples of the input
clock frequency. The SPLL reference clock (OSCCLK) can be generated from either of the
external clock sources described in Section 14.2.1, "External Reference Clocks."
The main purpose of the SPLL is to generate a stable reference frequency by multiplying
the frequency and eliminating the clock skew. The SPLL allows the processor to operate at
a high internal clock frequency using a low frequency clock input, providing two
advantages. First, lower frequency clock input reduces the overall electromagnetic
interference generated by the system. Second, the programmability of the oscillator enables
the system to operate at a variety of frequencies with only a single external clock source.
The MPC850 SPLL block diagram is shown in Figure 14-4.
OSCCLK
Feedback
C1
EXTAL
A5
Figure 14-3. Crystal Circuit Examples
Up
Phase
Down
Comparator
Clock
Delay
Figure 14-4. SPLL Block Diagram
Chapter 14. Clocks and Power Control
Crystal
R2 C2
R1
XTAL
A4
OSCM
XFC
Charge
VCO
Pump
V DDSYN / V SSSYN
Multiplication Factor
MF[0:11]
The Clock Module
VCOOUT