Freescale Semiconductor MPC850 User Manual page 47

Figure
Number
18-4 CP Command Register (CPCR)..................................................................................18-6
18-5 Dual-Port RAM Block Diagram ...............................................................................18-10
18-6 Dual-Port RAM Memory Map..................................................................................18-11
18-7 RISC Timer Table RAM Usage................................................................................18-14
18-8 RISC Timer Command Register (TM_CMD) ..........................................................18-15
18-9 RISC Timer Event Register (RTER)/Mask Register (RTMR) .................................18-16
19-1 MPC850 SDMA Data Paths .......................................................................................19-1
19-2 SDMA U-Bus Arbitration (Cycle Steal).....................................................................19-3
19-3 SDMA Configuration Register (SDCR) .....................................................................19-4
19-4 SDMA Status Register (SDSR) ..................................................................................19-4
19-5 DMA Channel Mode Register (DCMR).....................................................................19-7
19-6 IDMA Status Registers (IDSR1/IDSR2) ....................................................................19-8
19-7 IDMAx Channel's BD Table ......................................................................................19-9
19-8 IDMA Buffer Descriptor Structure...........................................................................19-10
19-9 Function Code Registers-SFCR and DFCR ...........................................................19-11
19-10 SDACK Timing Diagram: Single-Address
Peripheral Write, Externally-Generated TA .............................................................19-16
19-11 SDACK Timing Diagram: Single-Address
Peripheral Write, Internally-Generated TA ..............................................................19-17
19-12 SDACK Timing Diagram: Single-Address
Peripheral Read, Internally-Generated TA ...............................................................19-18
19-13 IDMA Channel Mode Register (DCMR) (Single-Buffer Mode) .............................19-19
19-14 IDMA1 Status Register (IDSR1) (Single-Buffer Mode) ..........................................19-20
19-15 Single-Address IDMA1 Burst Timing (Single-Buffer Mode)..................................19-21
20-1 MPC850 SI Block Diagram ........................................................................................20-2
20-2 Various Configurations of a TDM Channel................................................................20-5
20-3 Enabling Connections through the SI .........................................................................20-7
20-4 SI RAM Partitioning Using TDMa with Static Frames..............................................20-8
20-5 SI RAM Dynamic Changes with TDMa...................................................................20-10
20-6 SI RAM Partitioning Using TDMa with Dynamic Frames ......................................20-11
20-7 SIRAM Entry ............................................................................................................20-11
20-8 Example Using SI RAMn[SWTR] ...........................................................................20-12
20-9 SI Global Mode Register (SIGMR) ..........................................................................20-14
20-10 SI Mode Register (SIMODE) ...................................................................................20-15
20-11 One Clock Delay from Sync to Data (xFSD = 01) ...................................................20-17
20-12 No Delay from Sync to Data (xFSD = 00) ...............................................................20-17
20-13 Falling Edge (FE) Effect When CE = 1 and xFSD = 01...........................................20-17
20-14 Falling Edge (FE) Effect When CE = 0 and xFSD = 01...........................................20-18
20-15 Falling Edge (FE) Effect When CE = 1 and xFSD = 00...........................................20-19
20-16 Falling Edge (FE) Effect When CE = 0 and xFSD = 00...........................................20-20
20-17 SI Clock Route Register (SICR) ...............................................................................20-21
20-18 SI Command Register (SICMR)...............................................................................20-22
20-19 SI Status Register (SISTR) .......................................................................................20-22
ILLUSTRATIONS
Title
Illustrations
Page
Number
xlvii