Interrupt Queue Entry - Freescale Semiconductor MPC850 User Manual

Interrupt Queue Entry

Table 41-2. Serial ATM Event Register (SCCE) Field Descriptions (Continued)
Bits Name
14 GUN Global transmitter underrun. Indicates that an underrun occurred in the SCC's transmitter FIFO. A
GUN error is fatal because the affected channels are unknown. After GUN is set, the transmitter
stops data transmission from all channels and sets the APC disabled status flag APCST[DIS]. The
transmit line enters an idle state (logic high). After re-initializing the channels, the host may resume
transmission by issuing a
each channel.
For a faster recovery from a GUN error, re-initialize TSTATE by writing STFCR to the first byte,
clearing the second byte, and leaving the third and fourth bytes as is. Then the APC can be restarted
by clearing APCST[DIS]. This procedure results in corrupted transmit frames initially. (TSTATE
should normally be modified only during system initialization.) Note also that clearing APCST[DIS]
may be overwritten by the APC scheduling process; therefore, the user should verify that
APCST[DIS] has indeed been cleared after a minimum of 50 system clocks.
15 GOV Global receiver overrun. Indicates that an overrun occurred in the SCC's receiver FIFO. A GOV error
is fatal because the affected channels are unknown. After GOV is set, the receiver stops receiving
data from all channels and halts all data transfers to memory. After re-initializing the channels the
host may resume receiving by issuing a
Commands") for each channel.
For a faster recovery from a GOV error, re-initialize RSTATE by writing SRFCR to the first byte,
clearing the second byte, and leaving the third and fourth bytes as is. This procedure initially results
in corrupted receive frames which should be disposed of by software. (RSTATE should normally be
modified only during system initialization.)
41.2 Interrupt Queue Entry
Each entry in the ATM interrupt queue contains event information for a specific ATM
channel. During initialization, the host software should clear all queue entries and set the
wrap bit (W) only for the last entry. The format of an interrupt queue entry is shown in
Figure 41-4.
0 1 2 3
V W — CNG
Table 41-3 describes the fields of an interrupt queue entry.
Table 41-3. Interrupt Queue Entry Field Descriptions
Bit Name
0 V Valid bit. Indicates that this entry contains valid interrupt information. The CP sets this bit when
generating a new entry. The V bit and all event bits should be cleared by the host service routine
immediately after reading the entry.
1 W Wrap bit. Indicates the last entry in the interrupt queue. After the CP writes to this entry, it moves to
the beginning of the queue for the next event; that is, INTPTR is re-initialized to INTBASE. After the
host services this entry, it should move to the beginning of the queue for the next entry to be
processed; that is, the service pointer should be re-initialized to INTBASE. During initialization, the
host should set the W bit only for the last entry of the queue.
2 — Reserved
RESTART TRANSMIT
4 5 6 7 8 9
— APCO —
Figure 41-4. Interrupt Queue Entry
MPC850 Family User's Manual
Description
command (see Section 39.3, "ATM Commands") for
command (see Section 39.3, "ATM
RESTART RECEIVE
10 11 12 13
UN RXF BSY TXB
Description
14 15 16–31
RXB CHNUM_INDEX