Atm Event Registers; Utopia Event Register (Idsr1) - Freescale Semiconductor MPC850 User Manual

ATM Event Registers

After an interrupt request, the host's interrupt service routine polls the controllers' event
registers (SCCE[GINT] and/or IDSR1[GINT]) to determine which controller is requesting
service. After clearing GINT, the host processes each valid queue entry in turn, clearing
each V bit and all flagged event bits so that the entry can be reused by the CP. The host
continues servicing entries until it reaches an invalid entry (whose V bit is already cleared).
41.1 ATM Event Registers
The ATM event registers generate interrupts to the host and report on events that are
common to all channels of a controller. The global interrupt (GINT) bit indicates that at
least one channel-specific interrupt has been added to the interrupt queue. In UTOPIA
mode, the IDSR1 register is used as an exception event register; in serial ATM mode the
SCC event register (SCCE) is used for events.

41.1.1 UTOPIA Event Register (IDSR1)

The IDSR1 register is the ATM event register when operating in UTOPIA mode. IDSR1 is
used to report events and generate interrupt requests for the UTOPIA interface. Note that
in UTOPIA mode, interrupts from the ATM port are reported with an IDMA1 vector in the
CIVR, and the IDMA1 bit is set in the CIPR. Setting the corresponding bit in the mask
register IDMR1 enables the actual generation of the interrupt request. Event bits are cleared
by writing ones; writing zeros has no effect. The UTOPIA event and mask registers are
shown in Figure 41-2.
BIT 0
FIELD
Figure 41-2. UTOPIA Event Register (IDSR1) and Mask Register (IDMR1)
Table 41-1 describes the UTOPIA event register fields.
Table 41-1. UTOPIA Event Register (IDSR1) Field Descriptions
Bits Name
0–2 — Reserved
3 SYNC When this occurs the receiver stops receiving cells until it regains SOC synchronization.
SRSTATE[SNC] indicates that the receiver is waiting for resynchronization. Note that the
SYNC interrupt can be issued multiple times during the synchronization process until full
synchronization is achieved.
4 IQOV Interrupt queue overflow. Set by the CP whenever an overflow condition in the interrupt
queue occurs. This condition occurs if the CP attempts to write a new interrupt entry into a
valid entry (V = 1) not yet handled by the host.
5 GINT Global interrupt. Indicates that at least one new entry has been added to the interrupt queue.
After clearing the GINT event flag, the host begins processing the entries using the service
pointer. The host returns from the interrupt handler when it reaches an invalid queue entry (V
= 0).
1 2 3
— SYNC
Description
MPC850 Family User's Manual
4 5
IQOV GINT —
6 7
—