Smc Gci Event Register (Smce)/Mask Register (Smcm) - Freescale Semiconductor MPC850 User Manual

SMC in GCI Mode
30.5.9 SMC GCI Event Register (SMCE)/Mask Register
(SMCM)
The SMCE generates interrupts and reports events recognized by the SMC channel. When
an event is recognized, the SMC sets its corresponding SMCE bit. SMCE bits are cleared
by writing ones; writing zeros has no effect. SMCM has the same bit format as SMCE.
Setting an SMCM bit enables, and clearing an SMCM bit disables, the corresponding
interrupt Unmasked bits must be cleared before the CP clears the internal interrupt request
to the CP interrupt controller (CPIC). Figure 30-20 shows the SMCE/SMCM register
format.
Bit 0
Field
Reset
R/W
Address
Figure 30-20. SMC GCI Event Register (SMCE)/Mask Register (SMCM)
Table 30-23 describes SMCE/SMCM fields.
Bits Name
0–3 — Reserved, should be cleared.
4 CTXB C/I channel buffer transmitted. Set when the C/I transmit buffer becomes empty.
5 CRXB C/I channel buffer received. Set when the C/I receive buffer becomes full.
6 MTXB Monitor channel buffer transmitted. Set when the monitor transmit buffer becomes empty.
7 MRXB Monitor channel buffer received. Set when the monitor receive buffer becomes full.
1 2
—
0xA86 (SMCE1), 0xA96 (SMCE2)/ 0xA8A (SMCM1), 0xA9A (SMCM2)
Table 30-23. SMCE/SMCM Field Descriptions
MPC850 Family User's Manual
3 4
CTXB CRXB
0000_0000
R/W
Description
5 6
MTXB MRXB
7