Bisync Sync Register (Bsync) - Freescale Semiconductor MPC850 User Manual

Table 26-4 describes control character table and RCCM fields.
Table 26-4. Control Character Table and RCCM Field Descriptions
Offset Bit Name
0x42–0x50 0 E
1 B
2 H
3–7 —
8–15 CHARACTERn Control character 1–8. When using 7-bit characters with parity, include the
0x52 0–2 —
3–7 —
8–15 RCCM

26.7 BISYNC SYNC Register (BSYNC)

The BSYNC register defines BISYNC stripping and SYNC character insertion. When an
underrun occurs, the BISYNC controller inserts SYNC characters until the next buffer is
available for transmission. If the receiver is not in hunt mode when a SYNC character is
received, it discards this character if the valid bit (BSYNC[V]) is set.When using 7-bit
characters with parity, the parity bit should be included in the SYNC register value.
Bit 0 1 2
Field V 0 0
Reset
R/W
Address
End of table.
0 This entry is valid. The lower eight bits are checked against the incoming
character. In tables with eight control characters, E should be zero in all eight
positions.
1 The entry is not valid. No other valid entries exist beyond this entry.
BCS expected. A maskable interrupt is generated after the buffer is closed.
0 The character is written into the receive buffer and the buffer is closed.
1 The character is written into the receive buffer. The receiver waits for one
LRC or two CRC bytes of BCS and then closes the buffer. This should be
used for ETB, ETX, and ITB.
Hunt mode. Enables hunt mode when the current buffer is closed.
0 The BISYNC controller maintains character synchronization after closing this
buffer.
1 The BISYNC controller enters hunt mode after closing the buffer. When the B
bit is set, the controller enters hunt mode after receiving the BCS.
Reserved
parity bit in the character value.
All ones.
Reserved
Received control character mask. Masks comparison of CHARACTERn. Each
bit of RCCM masks the corresponding bit of CHARACTERn.
0 Mask this bit in the comparison of the incoming character and
CHARACTERn.
1 The address comparison on this bit proceeds normally and no masking
occurs. If RCCM is not set, erratic operation can occur during control
character recognition.
3 4 5 6
0 0 0 0
Undefined
SCC Base + 0x3E
Figure 26-3. BISYNC SYNC (BSYNC)
Chapter 26. SCC BISYNC Mode
BISYNC SYNC Register (BSYNC)
Description
7 8 9 10
0
R/W
11 12 13 14
SYNC
15