Translation Table Structure - Freescale Semiconductor MPC850 User Manual

The G attribute is used to map I/O devices that are sensitive to speculative
(out-of-order) accesses. An attempted speculative access to a page marked guarded
(G = 1) stalls until either the access is nonspeculative or is canceled by the core.
Attempting to fetch from guarded memory causes an implementation-specific
instruction TLB error interrupt.

8.7 Translation Table Structure

The MMU hardware supports a two-level software tablewalk. Other table structures are not
precluded. Figure 8-4 shows the two-level translation table when MD_CTR[TWAM] = 1
(4-Kbyte resolution of protection).
0
Level-1 Table Pointer (M_TWB)
20-Bit
Level-1 Table Base
20-Bit
20-Bit
20 for 4 Kbyte
18 for 16 Kbyte
13 for 512 Kbyte
Figure 8-4. Two-Level Translation Table (MD_CTR[TWAM] = 1)
19 0
Level-1 Table
Level-1 Descriptor 0
Level-1 Descriptor 1
Level-1 Descriptor N
Level-1 Descriptor 1023
Level-2 Table Base
20-Bit
9 for 8 Mbyte
Chapter 8. Memory Management Unit
Effective Address
9 10
Level-1 Index Level-2 Index
10-Bit
Level-1 Index 00
10-Bit
10-Bit
Level-2 Index
Level-2 Table
Level-2 Descriptor 0
Level-2 Descriptor 1
Level-2 Descriptor N
Level-2 Descriptor 1023
Physical Page Address
Physical Address
Translation Table Structure
19 20 31
Page Offset
12 for 4 Kbyte
14 for 16 Kbyte
19 for 512 Kbyte
23 for 8 Mbyte
00
10-Bit
Page Offset