Interface Configuration; General Atm Registers; Port D Pin Assignment Register (Pdpar) - Freescale Semiconductor MPC850 User Manual

Chapter 42
Interface Configuration
The following sections describe the programming of registers and parameters for ATM
operations through both the UTOPIA and serial interfaces.

42.1 General ATM Registers

This section describes the general ATM registers.

42.1.1 Port D Pin Assignment Register (PDPAR)

The ATM and UT bits have been added to the PDPAR register, shown in Figure 42-1. The
PDPAR register is cleared at system reset.
Bit 0 1
Field
ATM UT
Reset 0 0
Oper R/W R/W R/W
ADDR
Figure 42-1. Port D Pin Assignment Register (PDPAR)
The fields in the PDPAR register are described in Table 42-1.
Bits Name
0 ATM
1 UT
2 3 4 5
— DD3 DD4 DD5
0 0 0
R/W R/W R/W
OFFSET TO IMMR: 0X972 (PDPAR)
Table 42-1. PDPAR Field Descriptions
ATM global enable.
0 =Disable ATM SAR functionality
1 =Enable ATM SAR functionality
UTOPIA enable. Determines whether the parameter RAM's page 4 operates in serial or
UTOPIA mode.
0 =Serial ATM mode
1 = UTOPIA mode
Chapter 42. Interface Configuration
6 7 8 9
DD6 DD7 DD8 DD9
0 0 0 0
R/W R/W R/W R/W
Description
10 11 12 13
DD10 DD11 DD12 DD13
0 0 0 0
R/W R/W R/W R/W
14 15
DD14 DD15
0 0
R/W R/W