Features - Freescale Semiconductor MPC850 User Manual

Chapter 15
Memory Controller
The memory controller is responsible for controlling a maximum of eight memory banks
shared between a general-purpose chip-select machine (GPCM) and a pair of sophisticated
user-programmable machines (UPMs). It supports a glueless interface to SRAM, EPROM,
flash EPROM, regular DRAM devices, self-refresh DRAMs, extended data output DRAM
devices, synchronous DRAMs, and other peripherals. This flexible memory controller
allows the implementation of memory systems with very specific timing requirements.
The GPCM provides interfacing for simpler, lower-performance memory resources and
memory-mapped devices. The GPCM has inherently lower performance because it does
not support bursting. For this reason, GPCM-controlled banks are used primarily for
boot-loading and access to nonburstable memory-mapped peripherals.
The UPM provides both more features and, because it supports bursting, higher
performance. Therefore it is typically used to interface with higher-performance run-time
memory such as DRAM and bursting SRAM.
The UPM supports address multiplexing of the external bus, periodic timers, and
generation of programmable control signals for row address and column address strobes to
allow for a glueless interface to DRAM devices. The periodic timers allow refresh cycles
to be initiated while the address MUXing provides row and column addresses.
Different timing patterns can be generated for the control signals that govern a memory
device. These patterns define how the external control signals behave in read-access,
write-access, burst read-access, or burst write-access requests. Periodic timers are also
available to periodically generate user-defined refresh cycles.

15.1 Features

The following is a list of the memory controller's main features:
• Eight memory banks
— 32-bit address decode with mask
— Variable block sizes (32 Kbytes to 4 Gbytes)
— Byte parity generation/checking
Chapter 15. Memory Controller