High-Speed Irda Programming Example - Freescale Semiconductor MPC850 User Manual

High-Speed IrDA Programming Example

21. Write 0x20000000 to the CIMR to allow the SCC2 to generate a system interrupt.
The CICR should also be initialized.
22. Write 0x00000000 to GSMR_H[MODE] to enable normal behavior of CTS and CD
and idles between frames (as opposed to flags).
23. Write 0x00028800 to GSMR_L to configure CTS and CD to automatically control
transmission, reception (DIAG field), and HDLC mode. Normal operation of the
transmit clock is selected and the TCI bit is cleared. The TDCR and the RDCR must
be configured to 16x clock mode and the receiver decoding method must be NRZI.
Notice that the transmitter (ENT) and receiver (ENR) have not been enabled. For
inverted infrared operation, set GSMR_L[RINV, TINV].
24. Set the PSMR–HDLC to 0x1000 to configure two opening and one closing flag,
16-bit CCITT-CRC, and prevention of multiple frames in the FIFO.
25. Write 0x0108 for a 1.152 Mbps infrared rate or 0x0084 for a 0.576 Mbps infrared
rate to IRSIP. When working with timer 2 as the SIP trigger, the values should be
0x2108 for a 1.153 Mbps infrared or 0x2084 for a 0.572 Mbps.
26. Write 0x0003 to IRMODE to enable the infrared and to set the mode of operation to
middle-speed.
27. Program the TMR2 register when working with Timer 2 as the SIP trigger.
28. Write 0x00028830 to GSMR_L to enable the SCC2 transmitter and receiver. This
additional write ensures that the ENT and ENR bits are enabled last.
Note that after 5 bytes and CRC have been sent, the TxBD is automatically closed. Once a
complete frame is received, the RxBD is closed. Data received after 256 bytes or a single
frame causes a busy (out-of-buffers) condition since only one RxBD is prepared.
29.7 High-Speed IrDA Programming Example
High-speed infra-red programming is very similar to SCC transparent programming. The
parameter RAM programming and the RxBD and TxBD are the same as in the SCC
transparent mode, described in Chapter 28, "SCC Transparent Mode." The SCC2 and
infrared registers must be initialized. The following is an initialization sequence for a
high-speed infrared channel. The transmitter and receiver are both enabled. Both transmit
and receive clocks are provided externally to MPC850 using CLK3.
1. Configure the port A pins to enable the TXD2 and RXD2 pins. Set PAPAR[12,13]
and clear PADIR[12,13]. Clear PAODR[12,13].
2. Configure port A to enable CLK3. Set PAPAR[5]. Clear PADIR[5].
3. Connect CLK3 to SCC2 using the serial interface. Write SICR[R2CS] and
SICR[T2CS] to 0b110.
4. Connect the SCC2 to the NMSI (its own set of pins). Clear SICR[SC2].
5. Write the SDCR with the appropriate arbitration ID.
MPC850 Family User's Manual