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Bit
0
Field
Reset
R/W
Address
Figure 28-5. SCC Status Register in Transparent Mode (SCCS)
Table 28-10 describes SCCS fields.
Bit
Name
0–5
—
Reserved, should be cleared.
6
CS
Carrier sense (DPLL). Shows the real-time carrier sense of the line as determined by the DPLL.
0 The DPLL does not sense a carrier.
1 The DPLL senses a carrier.
7
—
Reserved, should be cleared.
28.14 SCC2 Transparent Programming Example
The following initialization sequence enables the transmitter and receiver, which operate
independently of each other. The sequence implements the connection shown for
MPC850(B) in Figure 28-1. The transparent controller is configured with RTS2 and CD2
active, and CTS2 is configured to be grounded internally in port C. CLK3 externally
provides the transmit and receive clocks. A 16-bit CRC-CCITT is sent with each
transparent frame. The FIFOs are configured for fast operation.
1. Configure port A to enable TXD2 and RXD2. Set PAPAR[12,13] and clear
PADIR[12,13] and PAODR[12,13].
2. Configure port C to enable RTS2, CTS2, and CD2. Set PCPAR[14] and PCSO[8,9]
and clear PCPAR[8,9] and PCDIR[8,9,14].
3. Configure port A to enable CLK3.Set PAPAR[5] and clear PADIR[5].
4. Connect CLK3 to SCC2 using the SI. Write 0b110 to SICR[R2CS] and
SICR[T2CS].
5. Connect the SCC2 to the NMSI (its own set of pins) and clear SICR[SC2].
6. Initialize the SDMA configuration register (SDCR) to 0x0001.
7. Write RBASE with 0x0000 and TBASE with 0x0008 in the SCC2 parameter RAM
to point to one RxBD at the beginning of dual-port RAM followed by one TxBD.
8. Write 0x0041 to CPCR to execute the
This command updates RBPTR and TBPTR of the serial channel with the new
values of RBASE and TBASE.
9. Write RFCR and TFCR with 0x10 for normal operation.
1
2
—
0xA37 (SCCS2), 0xA57 (SCCS3)
Table 28-10. SCCS Field Descriptions
Chapter 28. SCC Transparent Mode
SCC2 Transparent Programming Example
3
4
0000_0000
R
Description
INIT RX AND TX PARAMS
5
6
CS
—
command for SCC2.
7
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