Registers; Register List; Pll Control Register (Crpr) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

5.6 Registers

This section describes the registers of the CRG unit.
5.1.1.

Register list

Table 5-4 lists the CRG registers.
Table 5-4 CRG register list
Address
Base Offset
FFFE_7000 + 00 PLL control register
H H
+ 04 (Reserved)
H
+ 08 Watchdog timer control register
H
+ 0C Reset/Standby control register
H
+ 10 Clock frequency dividing control
H
register A
+ 14 Clock frequency dividing control
H
register B
+ 18 AHB(A) bus clock gate control
H
register
+ 1C APB(A) bus clock gate control
H
register
+ 20 APB(B) bus clock gate control
H
register
+ 24 AHB(B) bus clock gate control
H
register
+ 28 ARM core clock gate control
H
register
+ 2C DPERI0
H
register
+ 30 DPERI1
H
register
+ 34 Clock Selection Control register
H
(Reserved)
+ 35 – (Reserved)
H
+ 7F
H
+ 80 – SSCG registers
H
+ EF
H
+ F0 – (Reserved)
H
+ FF
H
Note
2
DPERI0 means the display peripherals of pixel output pipeline 0. These are color lookup table CLUT,
dither module DITH, signature module SIG and timing controller TCON
3
DPERI1 means the display peripherals of pixel output pipeline 1. These are color lookup table
CLUT, dither module DITH and signature module SIG
5-16
Abbreviatio
Register name
2
clock gate control
3
clock gate control
n
CRPR To control PLL
– Reserved area, access prohibited
CRWR To control watchdog timer
CRSR To control reset/standby
CRDA To control clock divider
CRDB To control clock divider
CRHA To control clock gate of AHB(A) bus
CRPA To control clock gate of APB(A) bus
CRPB To control clock gate of APB(B) bus
CRHB To control clock gate of AHB(B) bus
CRAM To control clock gate of ARM core
CRDP0 TO control clock gate of DPERI0
CRDP1 TO control clock gate of DPERI1
CSEL To control clock mutliplexers
– Reserved area, access prohibited
– see chapter SSCG (Spread Spectrum
Clock Generation)
– Reserved area, access prohibited
Explanation