Character Time-Out Interrupt - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

28.7.7 Character time-out interrupt

Character time-out interrupt occurs in the following cases:
• 1 or more data is stored in reception FIFO and the next serial data is still not received after 4
characters of time
• 1 or more data is stored in reception FIFO and CPU still does not read the data after 4
characters of time
When time-out interrupt occurs, INTR pin becomes "H". Moreover, XRXRDY signal becomes "L",
showing DMA controller that reception is ready, and requests to read data.
Timer and time-out interrupt are reset by CPU (or DMA controller) reading 1 byte from reception
FIFO. If time-out does not occur, it is reset after timer receives new data or CPU (or DMA
controller) reads data from reception FIFO.
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