Dram Ctrl Set Time1 Register (Drcst1) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

13.6.7 DRAM CTRL SET TIME1 Register (DRCST1)

This register sets access timing to DRAM. It should be set with correlation of internal clock
frequency and DRAM spec to be used.
Address
Bit 15 14 13
Name - TRCD
R/W R/W R/W
Initial value X 1 1
Bit field
No. Name
15 (Reserved)
14-12 TRCD
11 (Reserved)
10-8 TRAS
7 (Reserved)
13-10
F300_0000
12 11 10 9
- TRAS
R/W R/W
1 X 1 1
Reserved bit.
Write access is ignored.
RAS to CAS delay time (rRCD : Active to read or write command delay)
Bit[14:12] Delay time (number of
clock)
000 -
001 -
010 2
011 3
100 4
101 5
110 6
111 7
Reserved bit.
Write access is ignored.
RAS active time (rRAS : Active to precharge command)
Bit[10:8] Delay time (number of
clock)
000 -
001 5
010 6
011 7
100 8
101 9
110 10
111 11
Note 1: When 7 or less value is set, writing to DRAM is performed with tRAS
= 8
Reserved bit.
Write access is ignored.
+ 0A
H H
8 7 6 5
- TRP
R/W R/W
1 X 1 1
Description
Reserved
(Setting prohibited)
(Initial value)
Reserved
(Setting prohibited)
(Note 1)
(Initial value)
4 3 2 1
TRC
R/W
1 1 1 1
0
1