Soft Reset Register 2 For Macro (Cmsr2) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
Bit field
Number Name
2 SRST1_2 (CAN0
Soft Reset)
1 SRST1_1 (DDR2
Soft Reset)
0 SRST1_0 (GDC
Soft Reset)

7.4.20 Soft reset register 2 for macro (CMSR2)

Address
Bit 31 30 29
Name (Reserved)
R/W R R R
Initial value 0 0 0
Bit 15 14 13
(Reserv
Name SRST2_14 SRST2_13 SRST2_12 SRST2_11 SRST2_10 SRST2_9
ed)
R/W R/W R/W R/W
Initial value 0 0 0
Bit field
Number Name
31-9 (Reserved)
14 SRST2_14
(DPERI1 Soft
Reset)
Reset the CAN0 macro by writing "1" to this bit.
Set a '0' in this bit(field) during reset release.
0 No Soft Reset (initial value)
1 Soft Reset
Reset the DDR2 controller macro by writing "1" to this bit. Set a '0' in this bit(field) during reset
release.
0 No Soft Reset (initial value)
1 Soft Reset
Reset the GDC macro by writing "1" to this bit.
Set a '0' in this bit(field) during reset release.
0 No Soft Reset (initial value)
1 Soft Reset
FFF2_2000 + F8h
28 27 26 25
R/W R/W R/W R/W
0 0 0 0
12 11 10 9
R/W R/W R/W R/W
0 0 0 0
Reserved
Writes are ignored. Reads will return a '0' at all times.
Reset the DPERI1 macro by writing "1" to this bit.
Set a '0' in this bit(field) during reset release.
0 No Soft Reset (initial value)
1 Soft Reset
Function
24 23 22 21
R/W R/W R/W R/W
0 0 0 0
8 7 6 5
SRST2_8 SRST2_7 SRST2_6 SRST2_5
R/W R/W R/W R/W
0 0 0 0
Function
20 19 18 17
R/W R/W R/W R/W
0 0 0 0
4 3 2 1
SRST2_4 SRST2_3 SRST2_2 SRST2_1
R/W R/W R/W R/W
0 0 0 0
16
R/W
0
0
SRST2_0
R/W
0
7-33