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MB86R02 'Jade-D' Hardware Manual V1.64
34.5.6
TCON active Display Timing DISP0 Interface
The following values are only valid if the display clock is output at pin DCLKP/N, that means
ChanSel[i=0..12]=0. If the display clock is output at another pin of DISP0 Interface the timing values
might slightly differ.
Signal
Symbol
RSDS operation mode
DCLKP,
f_RSCK
DCLKN
t_RSCK
DISP0[11:0]P,
RSSU
DISP0[11:0]N
RSHD
RSSU
RSHD
TSG_[12:4],
TSIGSU
HSYNC0,
VSYNC0, DE0,
TSIGHD
GV0
TSIGSU
TSIGHD
TSIGSU
TSIGHD
TTL operation mode
DCLKP
f_TTLCK
t_TTLCK
DISP0[11:0]P,
DISPSU
DISP0[11:0]N
DISPHD
TSG_[12:4],
TSIGSU
HSYNC0,
VSYNC0, DE0,
GV0
TSIGHD
34-30
Description
Unit
Frequency
MHz
period
ns
setup time
ns
hold time
ns
setup time
ns
hold time
ns
setup time
ns
hold time
ns
setup time
ns
hold time
ns
setup time
ns
hold time
ns
Frequency
MHz
period
ns
setup time
ns
hold time
ns
setup time
ns
hold time
ns
min
max
Condition
55.5
18.0
C_L=30pF
2.7
C_L=30pF, Delay[i=12]=0,
2.9
Delay[i=0..11]=1
2.4
C_L=30pF, Delay[i=12]=1,
3.2
Delay[i=0..11]=0
C_L=30pF, Delay[i=12]=0,
7.4
Delay[i=0..11]=1;
7.4
SSWITCH[i]=0
C_L=30pF, Delay[i=12]=1,
11.9
Delay[i=0..11]=0;
2.9
SSWITCH[i]=0
C_L=30pF, Delay[i=12]=1,
2.9
Delay[i=0..11]=0;
11.9
SSWITCH[i]=1
55.5
18.0
C_L=tbd.
4.0
7.0
tbd
C_L=30pF, Delay[i=0..12]=0
5.0
7.0
C_L=130pF,
tbd
SSWITCH[i=0..12]=0
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