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MB86R02 'Jade-D' Hardware Manual V1.64
5.1.10.
AHB (B) bus clock gate control register (CRHB)
This register controls clock gate of AHB (B) bus.
Address
Bit
31
30
29
Name
–
–
–
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
X
X
X
Bit
15
14
13
Name
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
1
1
1
Bit field
No.
Name
31-16
–
15-0
HBGATE[15:0] HBCLK clock gate control
28
27
26
25
–
–
–
–
X
X
X
X
12
11
10
9
1
1
1
1
Unused bits.
Write access is ignored, and read value of these bits is undefined.
These bits control HBCLK clock gate.
HBGATE[n]
0
HBCLKn stops
1
HBCLKn does not stop (initial value)
HBCLK0: GDC (HOST IF)
HBCLK1: GDC (DRAW, GEO), MBUS2AXI (DRW)
HBCLK2: (Reserved)
HBCLK3: GDC (DISP0), MBUS2AXI (DISP)
HBCLK4: GDC (DISP1),
HBCLK5: GDC (CAP0), MBUS2AXI (CAP)
HBCLK6: GDC (CAP1)
HBCLK7: AXI, AHB2AXI, HBUS2AXI
HBCLK8: DDR2 controller, DDR2 I/F
HBCLK9: MLB (internal)
HBCLK10: (Reserved)
HBCLK11: (Reserved)
HBCLK12: (Reserved)
HBCLK13: (Reserved)
HBCLK14: (Reserved)
HBCLK15: (Reserved)
FFFE_7000
+ 24
H
H
24
23
22
21
–
–
–
–
X
X
X
X
8
7
6
5
HBGATE[15:0]
1
1
1
1
Description
Description
20
19
18
17
–
–
–
–
X
X
X
X
4
3
2
1
1
1
1
1
5-31
16
–
X
0
1
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