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MB86R02 'Jade-D' Hardware Manual V1.64
15.6.6 DMAC destination address register (DMACDAx)
ch0：FFFD0000+1C (h) ch1：FFFD0000+2C (h) ch2：FFFD0000+3C (h)
Address
ch4：FFFD0000+5C (h) ch5：FFFD0000+6C (h) ch6：FFFD0000+7C (h)
Bit
31
30
29
Name
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
0
0
0
Bit
15
14
13
Name
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
0
0
0
Bit field
No.
Name
31-0 DMACDA[31:0]
These bits are used to specify destination address to start DMA transfer, and they are
(DMAC
able to be read during DMA transfer.
Destination
When fixed address function (DMACB/FD) is disabled, these bits are incremented
Address)
according to the transfer width (DMACB/TB) after completing destination address
properly.
After DMA transfer, DMAC sets the next destination address to these bits.
[Note]
It is prohibited to set DMAC register address to DMACDA.
28
27
26
25
0
0
0
0
12
11
10
9
0
0
0
0
DMACDA
x(h)
Destination address to start DMA transfer
(Initial value: 32'h00000000)
(h)
(h)
24
23
22
21
DMACDA[31:16]
0
0
0
0
8
7
6
5
DMACDA[15:0]
0
0
0
0
Description
Function
ch3：FFFD0000+4C
ch7：FFFD0000+8C
20
19
18
17
0
0
0
0
4
3
2
1
0
0
0
0
15-15
16
0
0
0
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