Dma Configuration B Register (Dmacbx) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

15.6.4 DMA configuration B register (DMACBx)

ch0：FFFD_0000+14 (h) ch1：FFFD_0000+24 (h) ch2：FFFD_0000+34 (h)
Address
ch4：FFFD_0000+54 (h) ch5：FFFD_0000+64 (h) ch6：FFFD_0000+74 (h)
Bit 31 30 29
Name TT[1:0]
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W0 R/W0 R/W0
Initial value 0 0 0
Bit 15 14 13
Name SP[3:0]
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0
Bit field
No. Name
31-30 TT[1:0] These bits are used to specify transfer type. Currently, only 2 cycle transfer mode is
(Transfer Type) available for DMAC.
29-28 MS[1:0] These bits are used to select transfer mode.
(Mode Select)
27-26 TW[1:0] These bits are used to specify transfer data width.
(Transfer HSIZE of DMAC issues this value on AHB.
Width)
25 FS This bit is used to fix source address.
(Fixed Source) When the address needs to be added after each transfer, "0" must be set to this bit.
28 27 26 25
MS[1:0] TW[1:0] FS
0 0 0 0
12 11 10 9
DP[3:0]
0 0 0 0
TT[1:0]
0(h) 2 cycle transfer (initial value)
Other than
0(h)
MS[1:0]
0(h) Block transmission mode (initial value)
1(h) Burst transmission mode
2(h) Demand transmission mode
3(h)
TW[1:0]
0(h)
1(h)
2(h)
3(h)
FS
0(h) Source address is incremented (initial value)
1(h) Source address is fixed
FFFD_0000+44 (h)
FFFD_0000+84 (h)
24 23 22 21
FD RC RS RD
0 0 0 0
8 7 6 5
R R R
0 0 0 0
Description
Function
Reserved
Function
Reserved
Function
Byte (initial value)
Half-word
Word
Reserved
Function
ch3：
ch7：
20 19 18 17
EI CI SS[2:0]
0 0 0 0
4 3 2 1
(Reserved)
R R R R
0 0 0 0
15-11
16
0
0
R
0