Host Interface; Outline; Features; Limitations - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

16 Host Interface

This chapter describes the Host Interface of the MB86R02.
16.1.

Outline

The Host Interface module is an internal module connected to the AHB which is used for
communication to an external host CPU (which is connected via the SPI interface). The host
CPU can read and write to the internal module. From a host CPU point of view, this module
functions as a slave, whereas it functions as a master internally.
16.2.

Features

The Host Interface has the features described in the following sections.
16.2.1. Features
Accesses by the host CPU to the internal module can made using varying address bytes lengths
within a range of 1 to 4 bytes. Additionally, the data byte length can be arbitrarily set within a
range of 1 to 16 bytes. This means that the received number of bytes can be optimized and that
forwarding can be done efficiently. These settings can be specified by the CMD byte, allowing a
highly flexible solution that abstracts the type of host CPU in use and the access objects.

Supports communication to a host CPU with an SPI interface

The length of the SPI interface packets is variable to permit the use of variable length
addresses and data accesses

Supports writes/reads to the internal module connected to the AHB (variable, from 1 to 16
bytes)

Conforms to Freescale Semiconductor's advocacy SPI (CPOL=0, CPHA=0)

Corresponds to the speed of general purpose CPUs (set the frequency of SPICLK to 1/2 or
less of the HCLK frequency)

Host CPU handshaking communication makes software flow control possible
16.2.2.

Limitations


The MB86R02 can only operate in slave mode whereas the host CPU is the bus master

The packet sizes must be in 8 bit units

No CRC error detection functionality.

No automatic procedure for resends in the case of errors (no ARQ functionality)

Supported burst transfer modes for the AHB are single, incr or incr4
16-1