Bus Status Register (I2Cxbsr) - Fujitsu MB86R02 Jade-D Hardware Manual

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MB86R02 'Jade-D' Hardware Manual V1.64

29.7.2 Bus status register (I2CxBSR)

Initial value

All bits of this register are cleared when the EN bit of I2CxCCR is "0".

Bit 7: BB (bus busy)

This bit shows I

C bus state.

Stop condition is detected

Start condition is detected (but is in use)

Bit 6: RSC (Repeated Start Condition)

Repeated start condition detecting bit.

Repeated start condition is not detected

Start condition is detected again during bus is in use

This bit is cleared by writing "0" to the INT bit. Start condition detection at bus stop and stop

condition detection as well as addressing are not performed by the slave.

Bit 5: AL (Arbitration Lost)

Arbitration lost detection bit

Arbitration lost is not detected

Arbitration lost occurs during master transmission, or "1" is written to MSS bit

while other systems are using bus

This bit is cleared by writing "0" to the INT bit.

Restrictions:

In a multimaster environment, please prohibit other masters from transmitting general

call addresses simultaneously with this module, as well as using 'arbitration lost' for this

module at the second byte or later.

ch0：FFF5_6000 + 00h ch1：FFF5_7000 + 00h