Fujitsu MB86R02 Jade-D Hardware Manual page 177

MB86R02 'Jade-D' Hardware Manual V1.64
Table 9-5 List of register of IRC0
Address
Base Offset
FFFF_FE00 + 00 IRQ flag register
H H
or + 04 IRQ mask register
H
FFFE_8000
+ 08 Interrupt level mask register
H
H
+ 0C ICR monitoring register
H
+ 10 Hold request cancellation
H
level register
+ 14 Delay interrupt control
H
register
+ 18 (Reserved)
H
+ 1C Table base register
H
+ 20 Interrupt vector register
H
+ 24 IRQ test register
H
+ 28 FIQ test register
H
+ 2C (Reserved)
H
+ 30 Interrupt control register 0
H
+ 34 Interrupt control register 1
H
+ 38 Interrupt control register 2
H
+ 3C Interrupt control register 3
H
+ 40 Interrupt control register 4
H
+ 44 Interrupt control register 5
H
+ 48 Interrupt control register 6
H
+ 4C Interrupt control register 7
H
+ 50 Interrupt control register 8
H
+ 54 Interrupt control register 9
H
+ 58 Interrupt control register 10
H
+ 5C Interrupt control register 11
H
+ 60 Interrupt control register 12
H
+ 64 Interrupt control register 13
H
+ 68 Interrupt control register 14
H
+ 6C Interrupt control register 15
H
+ 70 Interrupt control register 16
H
+ 74 Interrupt control register 17
H
Register name Abbreviation
IRQF
IRQM
ILM
ICRMN
HRCL
DICR
TBR
VCT
IRQTEST
FIQTEST
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
ICR16
ICR17
Control of IRQ interrupt flag
The mask of the assert of the IRQ interrupt is controlled.
The interrupt level said to be valid from the ARM core is
set.
The interrupt level of a current IRQ interrupt source is
displayed.
The hold request cancellation level is set.
The delay interrupt for the task switch is controlled.
- It is a reserved area. (access prohibited)
The upper address of the IRQ vector (24 bits) is set.
Display the interrupt vector table.
The test of interrupt controller's IRQ interrupt function is
controlled.
- It is a reserved area. (access prohibited)
The level of the IRQ0 interrupt is set (unused and access
prohibited).
The level of the IRQ1 interrupt is set (unused and access
prohibited).
The level of the IRQ2 interrupt is set (unused and access
prohibited).
The level of the IRQ3 interrupt is set (unused and access
prohibited).
The level of the IRQ4 interrupt is set (unused and access
prohibited).
The level of the IRQ5 interrupt is set (IRC2 interrupt).
The level of the IRQ6 interrupt is set (IRC1 interrupt).
The level of the IRQ7 interrupt is set (GPIO interrupt).
The level of the IRQ8 interrupt is set (ADC ch.0 interrupt).
The level of the IRQ9 interrupt is set (ADC ch.1 interrupt).
The level of the IRQ10 interrupt is set (external interrupt
0).
The level of the IRQ11 interrupt is set (external interrupt
1).
The level of the IRQ12 interrupt is set (external interrupt
2).
The level of the IRQ13 interrupt is set (external interrupt
3).
The level of the IRQ14 interrupt is set (timer ch.0
interrupt).
The level of the IRQ15 interrupt is set (timer ch.1
interrupt).
The level of the IRQ16 interrupt is set (DMAC ch.0
interrupt).
The level of the IRQ17 interrupt is set (DMAC ch.1
interrupt).
Explanation
9-9