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MB86R02 'Jade-D' Hardware Manual V1.64
6.3.2 Global Address
For module base address refer to inter-module specification or global address map of the respective LSI.
6.3.3 Register Summary
Address
Base address +
0
H
Base address +
4
H
Base address +
8
H
Base address +
C
H
Base address +
14
H
Base address +
18
H
Base address +
1C
H
Base address +
20
H
Base address +
24
H
Base address +
SSCG_FREQUENCY_MEASUREMENT
2C
H
Base address +
30
H
Base address +
34
H
Base address +
44
H
Base address +
48
H
Register Description
SSCG_PERIOD
Register address
BaseAddress + 0
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field name
R/W
Reset value
Spread spectrum period
Bit
SSCG_PERIOD
11 -
Modulation period represented by 12 bits. The decimal value of the bits set to 1 multiplied by 256 sets the period in units of PLL clocks. Do not set
0
the period bits to a value below 64 (decimal)! The reset value = 74 (decimal) which yields a period of 35 KHz at 666MHz PLL clock). Setting
example, first 2 bits = 1 yields 3 (dec) * 256 (fixed) = modulation of 768 PLL clocks
SSCG_PERIOD_JITTER
Register address
BaseAddress + 4
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11
Field name
6-4
Register Name
SSCG_PERIOD
SSCG_PERIOD_JITTER
SSCG_FSTEP
SSCG_FOFFSET
SSCG_IEN
SSCG_InterruptStatus
SSCG_Status
SSCG_CTRL
SSCG_ENABLE
SSCG_COUNT_TYPE
SSCG_COUNT_TRIG
SSCG_CNTOUTFREQ
SSCG_RESET_CTRL
H
H
Description
Spread spectrum period
Alternative additional delta to SSCG_PERIOD
Rising/Falling frequency step on every PLL
clock cycle
Two's complement frequency offset to PLL
Clock
Interrupt Enable Register
Interrupt status register
Status register
SSCG control register
SSCG Start/Stop control register
Measurement position and measurement
duration
Measurement type
Trigger to start a measurement
Measurement result : Build average if
SSCG_CNT_AVERAGE = 1
Software Reset
10 9 8 7 6 5 4 3 2 1 0
SSCG_PERIOD
RW
4A
H
SSCG_PERIOD_JITTER
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