Fujitsu MB86R02 Jade-D Hardware Manual page 85

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MB86R02 'Jade-D' Hardware Manual V1.64

5. Watchdog reset

The watchdog timer starts when the WDTSET/WDTCLR bits of the watchdog timer control

bits a second time or at a later point in time clears the timer.

The clock source of the watchdog timer is the count value of the time based timer.

A clear operation of the time based timer effects the watchdog timer's count value.

When the timer is cleared, the watchdog timer is also cleared.

Selected time base timer bit

WDTCLR (max)

WDTCLR (min)

Watchdog reset request

As shown in Figure 5-2, a watchdog reset occurs after the second falling edge of the

selected time-based timer bit.

In ARM9 debug mode (DBGACK = 1)during PLL oscillation stabilization waiting time, CRG

clears the watchdog timer. In addition, it monitors the standby mode of the ARM9 core and

clears the watchdog timer automatically in standby mode (standby mode = 1.)

Reset output signal

The reset signal output by the reset generator is as follows depending on the reset source:

HRESETn (AHB/APB bus reset)

This internal reset signal initializes the ARM9 core and AHB/APB peripherals and is

output by an external reset, software reset or XSRST reset.

XSRST (reset monitoring)

This signal functions as a report to the external circuit of ARM's internal reset

source. This signal is asserted in the same way as the HRESETn signal.

Internal XTRST (built-in ICE macro reset)

This signal initializes the embedded macro of the ARM9 core. The macro must be

reset at power-on so that this signal is output by an external reset or an external

XTRST reset.

CRSTn (internal reset)

This signal is output by an external reset or an XSRST reset.

Figure 5-2 Watchdog reset timing