Dram Initialization Command Register [1] (Dric1); Dram Initialization Command Register [2] (Dric2) - Fujitsu MB86R02 Jade-D Hardware Manual

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MB86R02 'Jade-D' Hardware Manual V1.64

13.6.3 DRAM initialization command register [1] (DRIC1)

This register sets each control signal value of DRAM at the initialization operation.

When "1" is written to DRCMD in the initialization mode (DRINI = 1), the signal corresponding to

DRAM bus is driven by this setting value.

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Initial value

This register sets DRAM address signal value at the initialization operation.

When "1" is written to DRCMD in the initialization mode (DRINI = 1), the signal corresponding to

DRAM bus is driven by this setting value.

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Initial value

DRAM initialization method

All DRAM is initialized by CPU.

DDR2 controller is structured that each signal conductor necessary for the DRAM setting can be

driven by the register value in the initialization mode. Set certain value to this register

beforehand and "1" to command bit (DRCMD) to execute the setting command to DRAM.

To issue "Precharge all (PALL)" command to DRAM

1) Set "Bit[5:0] = 001000(b)" to DRAM initialization command register [1].

2) Set "Bit[13:0] = 00010000000000(b)" to DRAM initialization command register [2].

(Setting order of these 2 registers is not specified.)

3) Write "1" to bit 0 of DRAM initialization control register.

The value set at 1) and 2) is output to DRAM for 1ck period of time, and this

becomes command to DRAM.

• Command to DRAM without command execution in the initialization mode is NOP or

• For each control method of DRAM command and initialization, refer applied DRAM data

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