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MB86R02 'Jade-D' Hardware Manual V1.64
13.6.5 DRAM CTRL ADD register (DRCA)
This register sets items such as capacity of DRAM to be connected.
06
-0C
register settings related to DDR2 controller's DRAM operation should be fixed before
H
H
completing DRAM initialization.
Address
Bit
15
14
13
Bus1
Name
TYPE
6
R/W
R/W
R/W R/W R/W R/W
Initial value
1
1
0
Bit field
No.
Name
15-14
TYPE
13
Bus16
12-10
(Reserved)
9-8
BankRange
7-4
RowRange
3-0
ColRange
13-8
12
11
10
9
-
-
-
BankRange
X
X
X
0
Operation mode of DRAM control core is set.
11
DRAM control core operates in the DDR2SDRAM mode
Others Reserved (setting prohibited)
This specifies bus width of DRAM connected to external part.
0
32 bit
1
16 bit
Remark:
•
Use DQ[15:0], DQS0/1, and DM0/1
•
See the pin specifications for process of unused DQ[31:16], DQS2/3, and DM2/3
Reserved bits.
Write access is ignored.
Bank address is set.
Since only 4 banks are applied, these bits are ready only and fixed to 01(b.)
Row address range is set.
0001
4096 (12 bit)
0010
8192 (13 bit)
Others Reserved (setting prohibited)
Col address range is set.
0001
256 (8 bit)
0010
512 (9 bit)
0100
1024 (10 bit)
Others Reserved (setting prohibited)
F300_0000
+ 06
H
H
8
7
6
5
RowRange
R/W
R/W
1
0
0
1
Description
4
3
2
1
ColRange
R/W
0
0
0
1
0
0
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