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MB86R02 'Jade-D' Hardware Manual V1.64
Bit field
No.
Name
7
MLSB
6
TXDIS
5
RXDIS
4
SMPL
3
CPOL
2
FSPH
1
FSLN
0
FSPL
Note:
Do not overwrite CNTREG register when start bit of OPRREG register is "1".
27-10
Word bit's shift order is set.
0 Shift starts from MSB of the word
1 Shift starts from LSB of the word
Transmitting function is enabled or disabled.
0 Transmitting function is enabled
1 Transmitting function is disabled
Receiving function is enabled or disabled.
0 Receiving function is enabled
1 Receiving function is disabled
Sampling point of the data is specified.
0 Sampling at the center of reception data
1 Sampling at the end of reception data
I2S_SCKx polarity which drives/samples serial data is specified.
0 Data is driven at rising edge of I2S_SCKx, and sampled at falling edge
1 Data is driven at falling edge of I2S_SCKx, and sampled at rising edge
Phase is specified to I2S_WSx frame data.
0 I2S_WSx becomes valid 1 clock before the first bit of frame data
1 I2S_WSx becomes valid at the same time as the first bit of frame data
Pulse width of I2S_WSx is specified.
0 Pulse width is 1 cycle/I2S_SCKx long (1 bit)
1 Pulse width is 1 channel long (1 channel)
Setting "1" is prohibited when frame length is 1 channel long.
Polarity of I2S_WSx pin is set.
Frame synchronous signal becomes valid with I2S_WSx is "1"
0
The value is "0" at idle
Frame synchronous signal becomes valid with I2S_WSx is "0"
1
The value is "1" at idle
Description
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