Fujitsu MB86R02 Jade-D Hardware Manual page 180

MB86R02 'Jade-D' Hardware Manual V1.64
Address
Base Offset
+ 8C Interrupt control register 23
H
+ 90 Interrupt control register 24
H
+ 94 Interrupt control register 25
H
+ 98 Interrupt control register 26
H
+ 9C Interrupt control register 27
H
+ A0 Interrupt control register 28
H
+ A4 Interrupt control register 29
H
+ A8 Interrupt control register 30
H
+ AC Interrupt control register 31
H
Table 9-7 List of register of IRC2
Address
Base Offset
FFFB_1000 + 00 IRQ flag register
H H
+ 04 IRQ mask register
H
+ 08 Interrupt level mask register
H
+ 0C ICR monitoring register
H
+ 10 Holding request cancellation
H
level register
+ 14 Delay interrupt control
H
register
+ 18 (Reserved)
H
+ 1C Table base register
H
+ 20 Interrupt vector register
H
+ 24 IRQ test register
H
+ 28 FIQ test register
H
+ 2C (Reserved)
H
+ 30 Interrupt control register 0
H
+ 34 Interrupt control register 1
H
+ 38 Interrupt control register 2
H
+ 3C Interrupt control register 3
H
+ 40 Interrupt control register 4
H
+ 44 Interrupt control register 5
H
+ 48 Interrupt control register 6
H
+ 4C Interrupt control register 7
H
+ 50 Interrupt control register 8
H
+ 54 Interrupt control register 9
H
+ 58 Interrupt control register 10
H
9-12
Register name Abbreviation
ICR23
ICR24
ICR25
ICR26
ICR27
ICR28
ICR29
ICR30
ICR31
Register name Abbreviation
IRQF
IRQM
ILM
ICRMN
HRCL
DICR
TBR
VCT
IRQTEST
FIQTEST
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
Unused
The level of the IRQ24 interrupt is set (unused and
access prohibited).
The level of the IRQ25 interrupt is set (unused and
access prohibited).
The level of the IRQ26 interrupt is set (unused and
access prohibited).
The level of the IRQ27 interrupt is set (unused and
access prohibited).
The level of the IRQ28 interrupt is set (unused and
access prohibited).
The level of the IRQ29 interrupt is set (MLB_CINT
interrupt).
The level of the IRQ30 interrupt is set (MLB_SINT
interrupt).
The level of the IRQ31 interrupt is set (MLB_DINT
interrupt).
Control of IRQ interrupt flag
The mask of the assert of the IRQ interrupt is controlled.
The interrupt level said to be valid from the ARM core is
set.
The interrupt level of a current IRQ interrupt source is
displayed.
The holding request cancellation level is set.
The delay interrupt for the task switch is controlled.
- It is a reserved area. (access prohibited)
The upper address of the IRQ vector (24 bits) is set.
Display the interrupt vector table.
The test of interrupt controller's IRQ interrupt function is
controlled.
- It is a reserved area. (access prohibited)
The level of the IRQ0 (PWM ch 2)
The level of the IRQ1 (PWM ch 3)
The level of the IRQ2 ( PWM ch 4)
The level of the IRQ3 (PWM ch 5)
The level of the IRQ4 (PWM ch 6)
The level of the IRQ5 (PWM ch 7)
The level of the IRQ6 (ADC ch 2)
The level of the IRQ7 (ADC ch3)
The level of the IRQ8 (SPI ch 1)
The level of the IRQ9 (RLD)
The level of the IRQ10 (SIG ch 0)
Explanation
Explanation