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MB86R02 'Jade-D' Hardware Manual V1.64
9.5.2 IRQ flag register (IRQF)
The IRQF register controls the IRQ interrupt flag.
The IRQF bit is set as a result of the IRQ interrupt source level decision when the interrupt levels are
higher than the levels set in the ILM register, and the IRQ interrupt is asserted to the ARM core.
When "0" is writed to the IRQF register, the IRQ interrupt to the ARM core is negated. When the
IRQF bit is set, the interrupt vector is displayed in the VCT register.
The address value of the VCT register is not changed until the IRQF bit is set.
Address
FFFF_FE00
Bit
31
30
29
Name
-
-
-
R/W
R/W
R/W
R/W
Initial value
X
X
X
Bit
15
14
13
Name
-
-
-
R/W
R/W
R/W
R/W
Initial value
X
X
X
Bit field
Number
Name
31-1
-
0
IRQF
IRC0:
or FFFE_8000
+ 00
H
H
H
28
27
26
25
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
12
11
10
9
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
It is an unused bit.
The write access is ignored. The read value of these bits is undefined.
It is IRQ interrupt flag.
The IRQF bit is set in "1" as a result of the IRQ interrupt level decision when it is higher than the
level to which the interrupt level is set in the ILM register (Interrupt level of ICR register >
Interrupt level of ILM register), and IRQX (interrupt request) is asserted to the ARM core.
0 IRQ is not asserted.
1 IRQ is asserted.
This bit is cleared by writing "0". It is invalid to write "1".
IRC1:FFFB_0000
IRC2:FFFB_1000
24
23
22
21
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
8
7
6
5
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
Explanation
+ 00
H
H
+ 00
H
H
20
19
18
17
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
4
3
2
1
-
-
-
-
IRQF
R/W
R/W
R/W
R/W
X
X
X
X
16
-
R/W
X
0
R/W
0
9-15
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