Fujitsu MB86R02 Jade-D Hardware Manual page 276

MB86R02 'Jade-D' Hardware Manual V1.64
Bit field
No. Name
18-16 SS[2:0] These bits are used to show end code of DMA transfer which is shown below.
(Stop Status) These bits are also used to release interrupt (DIRQ) which is performed by writing 3'b000
to these bits when interrupt becomes error or it is issued by normal termination.
When various errors occur at the same time, end code is displayed by the following
priority.
15-12 SP[3:0] These bits are used to control source protection.
(Source HPROT at source access issues this value to AHB; however it is not performed if source
Protection) target does not equip protection function.
11-8 DP[3:0] These bits are used to control destination protection.
(Destination HPROT at destination access issues this value to AHB; however it is not performed if
Protection) source target does not equip protection function.
7-0 (Reserved) Reserved bits.
Write access is ignored. Read value of this bit is always "0".
SS Function
0(h) Initial value
1(h) Address overflow
2(h) Transfer stop request
3(h) Source access error
4(h) Destination access error
5(h) Normal termination
6(h) Reserved
7(h) DMA discontinuance
High priority
Reset
Clear by 3'b000 writing
Address overflow
Demand stop
Source access error
Destination access error
Low priority
SP
x(h) Protection code (initial value: 4'b0000.)
DP
x(h) Protection code (initial value: 4'b0000.)
Description
Status type
None
Error
Error
Error
Error
End
None
Function
Function
15-13