Sd Signal Timing; Clock; Input/Output Signal - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
34.5.15

SD Signal Timing

Hint: AC timing of SD Interface is not fully conform with SDMC Standard (Physical Layer) V1.0 .
34.5.15.1

Clock

Table 34-42 AC Timing of Clock Signal
Signal Name Symbol
SD_CLK t_CLK
*1: 20.83MHz for SD memory card and 20MHz for multimedia card (MMC)
34.5.15.2

Input/Output Signal

Table 34-43 AC Timing of Data Signal
Signal Name Symbol
SD_DAT[3:0],
tD_DAT
SD_CMD
SD_DAT[3:0],
tS_DAT
SD_CMD,
SD_XMCD,
tH_DAT
SD_WP
Load Capacitance 30pF
SD_CLK
SD_DAT[3:0]
SD_CMD
Figure 34-38 Output Timing to Media
SD _ CLK
SD_DAT[3:0]
SD _ DAT [ 3 : 0 ]
SD_CMD
SD_XMCD
SD_WP
Figure 34-39 Input Timing from Media
34-44
Description
SD_CLK cycle
Description
Output data delay (standard of SD_CLK
falling edge)
Input data setup (standard of SD_CLK
rising edge)
Input data hold (standard of SD_CLK
rising edge)
tD_DAT
VALID
DATA
tS _ DAT tH _ DAT
Value
Min. Typ.
– –
Value
Min. Typ.
-0.3 –
11.0 –
0.0 –
t_SDCLK
tD_DAT
VALID
DATA
tS _ DAT
Unit
Max.
20.83
MHz
(*1)
Unit
Max.
6.0 ns
– ns
– ns
tH _ DAT