Table of Contents
Advertisement
MB86R02 'Jade-D' Hardware Manual V1.64
29.8.3 Addressing
In master mode, the status is set to BB = "1" and TRX = "1" after a start condition occurs and the
contents of the I2CxDAR register are output starting with the MSB. When an acknowledge is received
from the slave after sending the address data, bit 0 of its data (I2CxDAR register's bit 0 after
transmission) is reversed and stored in the TRX bit.
In slave mode, the status is set to BB = "1" and TRX = "0" after a start condition occurs and transmission
data from the master is received in the I2CxDAR register. After receiving the address data, the
I2CxDAR and I2CxADR registers are compared. If they match the status is set to AAS = "1" and an
acknowledge is sent to the master. Then bit 0 of the reception data (I2CxDAR register's bit 0 after
reception) is stored in the TRX bit.
Example of a slave address transmission
Target slave address: 0x76 (Slave ADR register)
Send: 0xEC (Master DAR register)
Explanation: b1110 1100 (0xEC) is derived from b0111 0110 (0x76), left-shifted by 1 bit with a '0' added
as the LSB (see also format description below).
Transfer format of slave address
The transfer format of the slave address is shown below.
MSB
A6
A5
A4
Map of slave address
The slave address map is shown below.
Slave address
0000 000
0000 000
0000 001
0000 010
0000 011
0000 1XX
0001 XXX
1110 XXX
1111 0XX
1111 1XX
*1: This module does not support a 10 bit slave address
A3
A2
A1
Slave address
R/W
0
General call address
1
Start byte
X
CBUS address
X
Reserved
X
Reserved
X
X
Available slave address
X
10 bit slave address (*1)
X
Reserved
LSB
R/
ACK
A0
Description
29-23
Advertisement
Table of Contents
