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MB86R02 'Jade-D' Hardware Manual V1.64
LTS (display Transfer Stop)
Register
HostBaseAddress + 09
address
Bit number
7
Bit field name
R/W
Initial value
This register suspends DisplayList transfer.
Ongoing DisplayList transfer is suspended by setting LTS to "1".
LSTA (displayList transfer STAtus)
Register
HostBaseAddress + 10
address
Bit number
7
Bit field name
R/W
Initial value
This register indicates the DisplayList transfer status from Graphics Memory. LSTA is set to "1"
while DisplayList transfer is in progress. This status is cleared to 0 when DisplayList transfer is
completed
H
6
5
4
Reserved
R0
0
H
6
5
4
Reserved
R0
0
3
2
1
3
2
1
0
LTS
RW
0
0
LSTA
R
0
18-247
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