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MB86R02 'Jade-D' Hardware Manual V1.64
0:
Does not insert equalizing pulse into CCYNC signal
1:
Inserts equalizing pulse into CCYNC signal
Bit 13 to 8
SC (Scaling)
Divides display reference clock by the preset ratio to generate dot clock
Offset = 0
x00000
x00001
x00010
X00011
:
x11111
When n is set, with Offset = 0, the frequency division rate is 1/(2n + 2).
When m is set, with Offset = 100h, the frequency division rate is 1/(m + 1).
Basically, these are setting parameters with the same function (2n + 2 = m + 1).
Because of this, m = 2n + 1 is established. When n is set to the SC field with Offset =
0, 2n + 1 is reflected with Offset = 100h.
Also, when PLL is selected as the reference clock, frequency division rates 1/1 to 1/5
are non-functional even when set; other frequency division rates are assigned.
Bit 14
LCS (Lower Frequency Clock Select)
Predivide the clock signal for the dot clock
0:
The clock source for the scaler is the internal PLL clock.
1:
The clock source for the scaler is 1/4 of the frequency of the internal PLL clock.
This can be used to generate lower dot clock frequencies.
LCS=0 => Dot clock = (PLL clock)/(scaler)
LCS=1 => Dot clock = (PLL clock)/(scaler)/4
Bit 15
CKS (Clock Source)
Selects reference clock
0:
Internal PLL output clock
1:
DCLKI input
Bit 16
L0E (L0 layer Enable)
Enables display of the L0 layer. The L0 layer corresponds to the C layer for previous
products.
0:
1:
Bit 17
L1E (L1 layer Enable)
Enables display of the L1 layer. The L1 layer corresponds to the W layer for previous
products.
0:
1:
Bit 18
L23E (L2 & L3 layer Enable) ------ DCM0
Frequency not divided
Frequency division rate = 1/4
Frequency division rate = 1/6
Frequency division rate = 1/8
Frequency division rate = 1/64
Does not display L0 layer
Displays L0 layer
Does not display L1 layer
Displays L1 layer
Offset = 100
H
000000
Frequency not divided
000001
Frequency division rate = 1/2
000010
Frequency division rate = 1/3
000011
Frequency division rate = 1/4
:
111111
Frequency division rate = 1/64
18-67
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