Gdc Display Signal Timing; Clock; Input Signal - Fujitsu MB86R02 Jade-D Hardware Manual

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MB86R02 'Jade-D' Hardware Manual V1.64

GDC Display Signal Timing

Table 34-24 AC timing of Video Interface Clock Signal

Thdclki0 DCLKI H width

Thdclki1 DCLKI H width

DCLK (internal) Tldclk0

DCLK (internal) Tldclk1

*1: Internal display clock of PLL synchronization mode is generated by division of internal PLL in the display

clock prescaler.

*2: DCLKI or internal display clock of PLL is output.

*3: Load Capacitance 20pF

*4: Load Capacitance 30pF

1) Apply the signal only in PLL synchronization mode (CKS = 0)

(Reference clock = Clock output from internal PLL)

Table 34-25 AC Timing of Video Interface Input Signal (1)

2) Apply the signal only in DCLKI synchronization mode (CKS = 1)

(Reference clock = DCLKI)

Table 34-26 AC Timing of Video Interface Input Signal (2)

Twhsync0 HSYNC input pulse width

Tshsync0 HSYNC Input setup time

Thhsync0 HSYNC Input hold time

Twhsync1 HSYNC input pulse width

Tshsync1 HSYNC Input setup time

Thhsync1 HSYNC Input hold time

DCLKI frequency

DCLKI L width

DCLKI frequency

DCLKI L width

DCLK frequency *1

DCLKO frequency*3

DCLKO frequency*4

HSYNC input pulse width

VSYNC input pulse width