Fujitsu MB86R02 Jade-D Hardware Manual page 95

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MB86R02 'Jade-D' Hardware Manual V1.64

PLLBYPASS bit becomes "0". Also, the PLL oscillation stabilization waiting state

is skipped if PLLMODE[4:0] is 5'b11111.

* STOP = CLK clock is able to stop while the value is "1"

Figure 5-13 Stop mode

PLL oscillation

stabilization waiting