Fujitsu MB86R02 Jade-D Hardware Manual page 93

MB86R02 'Jade-D' Hardware Manual V1.64
0 0 0
0 0 0
0 0 1
0 0 1
320M
0 0 1
0 0 0
0 1 0
0 0 0
266M
0 0 1
0 0 0
1 1 1
PLLBYPASS
CLK
1/M PLL clock
CCLK
PLLREADY
PLLBYPASS
1 0 32 1
1 1 33 1
0 0 61 3
0 1 51 2
1 0 92 3
1 0 32 1
0 0 17 1
0 0 64 3
0 1 51 2
0 1 80 3
1 1 PLLSTOP
The main clock (CCLK) of the CRG module can be dynamically switched between
the PLL clock and an external input clock (CLK) using PLLBYPASS bit of the PLL
control register (CRPR).
Clock switching
a)
Figure 5-10 Clock switching between the PLL clock / external clock
20.8333 666.67 333.33
20.00 660.00 330.00
31.25 635.42 317.71
25.00 637.50 318.75
20.8333 638.89 319.44
20.00 640.00 320.00
31.25 531.25 265.63
25.00 533.33 266.67
20.8333 531.25 265.62
20.00 533.33 266.67
a) Clock source change (write PLLBYPASS bit (write 0))
b) Clock source change (write PLLBYPASS bit (write 1))
333.33 166.67 83.33
330.00 165.00 82.50
317.71 158.85 79.43
318.75 159.38 79.69
319.44 159.72 79.86
320.00 160.00 80.00
265.63 132.81 66.41
266.67 133.33 66.67
265.62 132.81 66.41
266.67 133.33 66.67
Clock switching
b)
166.67 41.67
165.00 41.25
158.85 39.71
159.38 39.84
159.72 39.93
160.00 40.00
132.81 33.20
133.33 33.33
132.81 33.20
133.33 33.33
5-13