I2C Bus Timing - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
34.5.11

I2C Bus Timing

Table 34-33 AC timing of I
Signal Symbol
SDAI setup
T
S2SDAI
time
I2C_SDA0 SDAI hold
T
H2SDAI
I2C_SDA1 time
T BUS free time
WBFI
SCLI cycle
T
CSCLI
time
T SCLI H width
WHSCLI
T SCLI L width
WLSCLI
SCLO cycle
T
CSCLO
time
I2C_SCL0
I2C_SCL1
T SCLO H width
WHSCLO
T SCLO L width
WLSCLO
SCLI setup
T
S2SCLI
time
T SCLI hold time
H2SCLI
2
*1: I C bus specification value
2
*2: See I C bus interface's clock control register (I2CxCCR) of the MB86R02 LSI product specifications for the
"m" value
*3: PCLK = APB bus clock cycle
STOP
I2C_SDA0(in)
I2C_SDA1(in)
T
S2SCLI
I2C_SCL0(in)
I2C_SCL1(in)
STOP
I2C_SDA0(out)
I2C_SDA1(out)
T
S2SCLO
I2C_SCL0(out)
I2C_SCL1(out)
2
Figure 34-33 I C Access Timing
34-38
2
C signal
Description
Normal mode
High-speed mode
Normal mode
High-speed mode
Normal mode
High-speed mode
Normal mode
High-speed mode
Normal mode
High-speed mode
Normal mode
High-speed mode
Normal mode
High-speed mode
Normal mode
High-speed mode
Normal mode
High-speed mode
Normal mode
High-speed mode
Normal mode
High-speed mode
START
D7 D6 D5
T T T
H2SCLI S2SDAI H2SDAI
T
WBFI
START
D7 D6 D5
T T
H2SCLO H2SDAO
Value
Min.
250 (*1)
100 (*1)
0.0 (*1)
0.0 (*1)
4.7 (*1)
1.3 (*1)
1.0 (*1)
2.5 (*1)
4.0 (*1)
0.6 (*1)
4.7 (*1)
1.3 (*1)
2*m + 2 (*2)
Int (1.5*m) + 2 (*2)
m + 2 (*2)
Int (0.5*m) + 2 (*2)
m (*2)
m (*2)
4.0 (*2)
0.6 (*2)
4.7 (*2)
1.3 (*2)
D4 D3 D2 D1 D0
T T T
CSCLI WHSCLI
D4 D3 D2 D1 D0
T T T
CSCLO WHSCLO
Unit
Typ. Max.
– – ns
– – ns
– – ns
– – ns
– – µs
– – µs
– – µs
– – µs
– – µs
– – µs
– – µs
– – µs
– – PCLK (*3)
– – PCLK (*3)
– – PCLK (*3)
– – PCLK (*3)
– – PCLK (*3)
– – PCLK (*3)
– – µs
– – µs
– – µs
– – µs
RESTART
ACK
T T
S2SCLI H2SCLI
WLSCLI
RESTART
ACK
T T
S2SCLO H2SCLO
WLSCLO