External Interrupt Request Register (Eireq) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

10.5.3 External interrupt request register (EIREQ)

This register is to indicate and clear external interrupt request.
Address
Bit 31 30 29
Name – – –
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value X X X
Bit 15 14 13
Name – – –
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value X X X
Bit field
No. Name
31-8 –
7-4 –
3-0 REQ3-0
10-6
FFFE_4000
28 27 26 25
– – – –
X X X X
12 11 10 9
– – – –
X X X X
Unused bit.
Write access is ignored. Read value of these bits is undefined.
Unused bit.
Write access is ignored. Read value of these bits is always "0".
External interrupt request is indicated and cleared.
At reading:
0
At writing: External interrupt request is cleared
At reading:
1
At writing: External interrupt request invalid
Read value of "1" shows external interrupt is requested. These bits correspond to
external interrupt channel as follows.
REQ0: External interrupt 0 (INT_A[0] pin)
REQ1: External interrupt 1 (INT_A[1] pin)
REQ2: External interrupt 2 (INT_A[2] pin)
REQ3: External interrupt 3 (INT_A[3] pin)
When "0" is written to these bits, external interrupt request is cleared.
Writing "1" is invalid. These bits are initialized to "0000
+ 04
H H
24 23 22 21
– – – –
X X X X
8 7 6 5
– – – –
R0 R0 R0
X 0 0 0
Description
There is no external interrupt request
There is external interrupt request
20 19 18 17
– – – –
X X X X
4 3 2 1
REQ REQ REQ REQ
–
3 2 1
R0 R/W0 R/W0 R/W0 R/W0
0 0 0 0
" by reset.
B
16
–
X
0
0
0