Fujitsu MB86R02 Jade-D Hardware Manual page 674

MB86R02 'Jade-D' Hardware Manual V1.64
RSCKH RSCKL
RSCK (pin DISP[j])
diff.
50%
Register DIR_Pin_ctrl[j].Delay=0
RSDAT (pins DISP[i])
0V diff.
Registers DIR_Pin_ctrl[i].Delay=1
RSSU RSHD
RSSU RSHD
TSIGSU TSIGHD
Pins TSIG[i]
TTL
Register Dir_SSwitch.SSwitch =0
Figure 22-9 RSDS operation Output Timing
Figure 22-10 Rise Fall Times
22-40