Endian And Byte Lane To Each Access - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

11.9.3 Endian and byte lane to each access

The external bus interface corresponds to both little endian and big endian. These switches are
set with external pin, BIGEND. External data bus width is set with external pin,
MPX_MODE_1[1:0].
Correlation of each endian, external data bus width, and byte lane to each access is shown
below.
Table 11-2 Relation of byte lane at little endian
Endian Access MPX_MODE_
(BIGEND) size 1[1:0]
16 bit
( ≠ 2'b01)
Word
32 bit
(=2'b01)
16 bit
( ≠ 2'b01)
Half-Word
Little
32 bit
(=1'b0)
(=2'b01)
16 bit
( ≠ 2'b01)
Byte
32 bit
(=2'b01)
H*DATA: HWDATA or HRDATA is internal signals
11-18
Target width Internal bus Enabled byte lane
(WDTH) address
MEM_ED[7:0]
MEM_ED[7:0]
8bit 0
MEM_ED[7:0]
MEM_ED[7:0]
MEM_ED[15:0]
16bit 0
MEM_ED[15:0]
32bit(prohibited) -
MEM_ED[7:0]
MEM_ED[7:0]
8bit 0
MEM_ED[7:0]
MEM_ED[7:0]
MEM_ED[15:0]
16bit 0
MEM_ED[15:0]
32bit 0 MEM_ED[31:0]
0 MEM_ED[7:0]
MEM_ED[7:0]
8bit
2 MEM_ED[7:0]
MEM_ED[7:0]
0 MEM_ED[15:0]
16bit
2 MEM_ED[15:0]
32bit(prohibited) -
0 MEM_ED[7:0]
MEM_ED[7:0]
8bit
2 MEM_ED[7:0]
MEM_ED[7:0]
0 MEM_ED[15:0]
16bit
2 MEM_ED[15:0]
0 MEM_ED[15:0]
32bit
2 MEM_ED[31:16]
0 MEM_ED[7:0]
1 MEM_ED[7:0]
8bit
2 MEM_ED[7:0]
3 MEM_ED[7:0]
0 MEM_ED[7:0]
1 MEM_ED[15:8]
16bit
2 MEM_ED[7:0]
3 MEM_ED[15:8]
32bit(prohibited) -
0 MEM_ED[7:0]
1 MEM_ED[7:0]
8bit
2 MEM_ED[7:0]
3 MEM_ED[7:0]
0 MEM_ED[7:0]
1 MEM_ED[15:8]
16bit
2 MEM_ED[7:0]
3 MEM_ED[15:8]
0 MEM_ED[7:0]
1 MEM_ED[15:8]
32bit
2 MEM_ED[23:16]
3 MEM_ED[31:24]
Corresponding internal
bus data
st
1 : H*DATA[7:0]
nd
2 : H*DATA[15:8]
rd
3 : H*DATA[23:16]
th
4 : H*DATA[31:24]
st
1 : H*DATA[15:0]
nd
2 : H*DATA[31:16]
- -
st
1 : H*DATA[7:0]
nd
2 : H*DATA[15:8]
rd
3 : H*DATA[23:16]
th
4 : H*DATA[31:24]
st
1 : H*DATA[15:0]
nd
2 : H*DATA[31:16]
H*DATA[31:0]
st
1 : H*DATA[7:0]
nd
2 : H*DATA[15:8]
st
1 : H*DATA[23:16]
nd
2 : H*DATA[31:24]
H*DATA[15:0]
H*DATA[31:16]
- -
st
1 : H*DATA[7:0]
nd
2 : H*DATA[15:8]
st
1 : H*DATA[23:16]
nd
2 : H*DATA[31:24]
H*DATA[15:0]
H*DATA[31:16]
H*DATA[15:0]
H*DATA[31:16]
H*DATA[7:0]
H*DATA[15:8]
H*DATA[23:16]
H*DATA[31:24]
H*DATA[7:0]
H*DATA[15:8]
H*DATA[23:16]
H*DATA[31:24]
- -
H*DATA[7:0]
H*DATA[15:8]
H*DATA[23:16]
H*DATA[31:24]
H*DATA[7:0]
H*DATA[15:8]
H*DATA[23:16]
H*DATA[31:24]
H*DATA[7:0]
H*DATA[15:8]
H*DATA[23:16]
H*DATA[31:24]
MEM_XWR MEM_XWR MEM_EA[1]
[3:2] [1:0]
0
0
not active 10
1
1
0
not active 00
1
- - -
0
not active
0
10
1
not active
1
0
not active 00
1
00 00 0
0
not active 10
0
1
not active 10
1
0
not active 00
not active 00 1
- - -
0
not active 10
0
1
not active 10
1
0
not active 00
not active 00 1
11 00 0
00 11 0
not active 10 0
not active 10 0
not active 10 1
not active 10 1
not active 10 0
not active 01 0
not active 10 1
not active 01 1
- - -
not active 10 0
not active 10 0
not active 10 1
not active 10 1
not active 10 0
not active 01 0
not active 10 1
not active 01 1
11 10 0
11 01 0
10 11 0
01 11 0