Fujitsu MB86R02 Jade-D Hardware Manual page 73

MB86R02 'Jade-D' Hardware Manual V1.64
core supply a protection by a filter is
recommended.
SSCG Supply (seperated ground plane
recommented, connection via filter to digital
#SSCGVSS ground)
VINITHI
CLK_SEL Select Pin for emb. Crystal CLK or ECLK
ECLK External Clock Source (selected by CLK_SEL)
CRIPM0
CRIPM1
CRIPM2
CRIPM3
OSC_FILTER characteristic of post-oscillator filter
OSC_MODE1 oscillator mode 1
OSC_BIAS0 Oscillator bias level 0
OSC_BIAS1 Oscillator bias level 1
OSC_MODE0 oscillator mode 0
XRST System Reset
PLLTDTRST PLL Transition Delay Test Reset ????
XTRST Test reset
UART_SIN0 UART0 serial input
UART_SOUT0 UART0 serial output
UART_XCTS0 UART0 Clear to send
UART_XRTS0 UART0 Request to send
UART_SIN1 UART1 serial input
UART_SOUT1 UART1 serial output
UART_SIN2 UART2 serial input
UART_SOUT2 UART2 serial output
n/a
Connect to VSS
Pull down to VSS through high resistance for
embedded OSC or
Pull up to VDDE through high resistance for
external OSC (clock input ECLK)
Pull up to VDDE or pull down to VSS through high
resistance
Pull up to VDDE or pull down to VSS through high
resistance
Pull up to VDDE or pull down to VSS through high
resistance
Pull up to VDDE or pull down to VSS through high
resistance
Pull up to VDDE or pull down to VSS through high
resistance
Connect to VDDE (3.3V) via a high resistance
Connect to VSS
Connect to VSS
Connect to VSS
Connect to VSS
n/a
Keep the pin open
n/a
Keep the pin open
Pull up to VDDE or pull down to VSS through high
resistance
Keep the pin open
Pull up to VDDE or pull down to VSS through high
resistance
Keep the pin open
Pull up to VDDE or pull down to VSS through high
resistance
Keep the pin open
Pull up to VDDE or pull down to VSS through high
resistance
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