Fujitsu MB86R02 Jade-D Hardware Manual page 798

MB86R02 'Jade-D' Hardware Manual V1.64
Bit 0: INT (INTerrupt)
This is the transfer end interrupt request flag bit.
On writes
INT
0 Transfer end interrupt flag is cleared
1 N/A
On reads
INT
0 Transfer has not completed
This is set when following conditions are applied on the completion of a 1 byte
transfer which includes the acknowledge bit.
•
Bus master
•
Addressed slave
1
•
General call address is received (only at GCAA ＝ "1")
•
Arbitration lost occured (only at bus acquisition state)
•
Start condition attempted while other systems are using the bus
When this bit is "1", the SCL line is held at the "L" level. This is cleared by writing "0" to this bit,
then the SCL line opens and the next byte is transferred. In addition, this is cleared to "0" by an
occurrence of a start condition or a stop condition in master mode.
Competition of SCC, MSS, and INT bits
Competition of the next byte transfer, start condition, and stop condition occurs by writing to the
SCC, MSS, and INT bits simultaneously. The priority order in this case is as follows:
1. Occurrence of the next byte transfer and stop condition
When writing "0" to the INT bit and the MSS bit simultaneously, the MSS bit is prioritized and
a stop condition occurs.
2. Occurrence of the next byte transfer and start condition
When writing "0" to the INT bit and "1" to the SCC bit simultaneously, the SCC bit is prioritized
and a start condition occurs.
3. Occurrence of start condition and stop condition
Writing "1" to the SCC bit and "0" to the MSS bit simultaneously is prohibited.
State
State
29-11