Video Output Limitation; Interrupt - Fujitsu MB86R02 Jade-D Hardware Manual

Graphics controller
Hide thumbs Also See for MB86R02 Jade-D:
Table of Contents

Advertisement

MB86R02 'Jade-D' Hardware Manual V1.64
display controller 0 is demultplexed internally and output on the two video output ports. Two video
output ports are used only for display controller 0 so display controller 1 can not be used.
DCM1
DEN-bit
DISP0
1
DISP1
0
Common
VCCC/dis2s=1
Note that the external synchronization mode of display controller 1 has to be disabled to output
HSYNC1 and VSYNC1.
Multiplex dual display (external demultiplex)
In the case of multiplex dual display with an external demultiplexer, one or both display controllers can
be used. The example shows display controller 0 in use in single display mode and display controller 1
in use in multiplex dual display mode.
DCM1
DEN-bit
DISP0
1
DISP1
1
Common
If two display controllers are used in multiplex dual display mode, four display screens can be used.
18.6.11

Video output limitation

Due to the limited number of package pins, the available video output is limitted as follows.
Display controller 0: RGB888 (R[7:0], G[7:0], B[7:0])
Display controller 1: RGB666 (R[7:2], G[7:2], B[7:2])
See "Pin Multiplex Mode" for details.
18.6.12

Interrupt

The primary interrupt functions for Jade-D display and capture are the same as for Coral PA except
that there are two controllers. The IST (interrupt status register) bit allocation is as follows:
bit 0
CERR (Command Error Flag)
bit 1
CEND (Command End)
bit 2
VSYNC0 of display 0
bit 3
FSYNC0 of display 0
bit 4
SYNCERR0 of display 0
bit 5
REGUD0 of display 0
bit 6
VSYNC1 of display 1
bit 7
FSYNC1 of display 1
DCM3
POM-bit
DCKed-bit
1
1
Don't care
Don't care
DCM3
POM-bit
DCKed-bit
0
0
0
0
VCCC/dis2s=0
MDC
MDen-bit
SCnEN-field
1
Valid
Don't care
Don't care
MDC
MDen-bit
SCnEN-field
0
Don't care
1
Valid
18-35

Advertisement

Table of Contents
loading

Table of Contents