Fujitsu MB86R02 Jade-D Hardware Manual page 410

MB86R02 'Jade-D' Hardware Manual V1.64
CCLK0/1
More than 1 CCLK0/1
HSYNCI
HSYNC(internal
RGB input
function)
Note: The maximum horizontal enable area size (RGBHEN) which can be captured is 840 pixels.
This is the restriction by line buffer size in a video capture module.
(2) Valid data input rule to HSYNC
A valid image data input rule to HSYNC is shown.
Data is input in sync with the HSYNC of each line as the sampling clock of image data is generated
using HSYNC and a clock could have line jitter.
CCLK1
HSYNCI
RI5-0
GI5-0
BI5-0
(3) VINVSYNC Polarity and Rules
A VSYNCI signal is in sync with HSYNCI. VSYNCI is sampled by HSYNCI and is used as a
VSYNC signal. Its width is at least one line or more although a VSYNCI signal does not need to
synchronize with HSYNC at this time.
Both the positive and negative edges of VSYNCn can be used as a vertical sync. This is
determined using the RGBS (RGB Input Sync) register setup: VSYNCI Polarity (VP).
1RGBCLK
HSYNC(internal RGB
input function)
VSYNCI
(4) Valid line input rule for VSYNC
The valid image data input rule for VSYNC is shown below.
18-52
∬
∬
∬
~840CCLK0/1+α(HBLANK)
RGBHST
~840RGBCLK+αRGBCLK
More than 1 line
∬
∬
∬
captured