Fujitsu MB86R02 Jade-D Hardware Manual page 11

MB86R02 'Jade-D' Hardware Manual V1.64
8.6.4 INITRAM control ............................................................................................................. 8-9
9 Interrupt Request Controller (IRC) ................................................................................................ 9-1
9.1 Overview ............................................................................................................................. 9-1
9.2 Features ............................................................................................................................. 9-1
9.3 Interrupt map ...................................................................................................................... 9-2
9.3.1 Exception vector to ARM926EJ-S core .......................................................................... 9-2
9.3.2 Expansion IRQ interrupt vector of IRC0/IRC1 ................................................................ 9-3
9.3.3 Interrupt request connection diagram ............................................................................. 9-6
9.4 Block diagram ..................................................................................................................... 9-7
9.5 Register .............................................................................................................................. 9-8
9.5.1 Register list ..................................................................................................................... 9-8
9.5.2 IRQ flag register (IRQF) ................................................................................................ 9-15
9.5.3 IRQ mask register (IRQM) ............................................................................................ 9-16
9.5.4 Interrupt level mask register (ILM) ................................................................................ 9-16
9.5.5 ICR monitoring register (ICRMN).................................................................................. 9-18
9.5.6 Holding request cancellation level register (HRCL) ...................................................... 9-19
9.5.7 Delay interrupt control register (DICR) ......................................................................... 9-20
9.5.8 Table base register (TBR) ............................................................................................ 9-21
9.5.9 Interrupt vector register (VCT) ...................................................................................... 9-22
9.5.10 IRQ test register (IRQTEST) ......................................................................................... 9-23
9.5.11 FIQ test register (FIQTEST) ......................................................................................... 9-24
9.5.12 Interrupt control register (ICR31-ICR00) ...................................................................... 9-25
9.6 Operation explanation ...................................................................................................... 9-27
9.6.1 Outline of operation ...................................................................................................... 9-27
9.6.2 Initialization ................................................................................................................... 9-27
9.6.3 Multiple interrupt processing ......................................................................................... 9-28
9.6.4 Example of IRQ interrupt handler ................................................................................. 9-28
9.6.5 Stop and return from sleep mode ................................................................................. 9-30
9.6.6 Notes on use of IRC ..................................................................................................... 9-31
10 External Interrupt Controller (EXIRC) ...................................................................................... 10-1
10.1 Outline .............................................................................................................................. 10-1
10.2 Feature ............................................................................................................................. 10-1
10.3 Block diagram ................................................................................................................... 10-2
10.4 Supply clock ..................................................................................................................... 10-2
10.5 Register ............................................................................................................................ 10-3
10.5.1 Register list ................................................................................................................... 10-3
10.5.2 External interrupt enable register (EIENB) ................................................................... 10-5
10.5.3 External interrupt request register (EIREQ) .................................................................. 10-6
10.5.4 External interrupt level register (EILVL) ........................................................................ 10-7
10.6 Operation .......................................................................................................................... 10-8
10.7 Operation procedure ........................................................................................................ 10-8
10.8 Instruction for use ............................................................................................................. 10-8
11 External Bus Interface ............................................................................................................. 11-1
11.1 Outline .............................................................................................................................. 11-1
11.2 Features ........................................................................................................................... 11-1
11.3 Block diagram ................................................................................................................... 11-1
11.4 Related pin ....................................................................................................................... 11-2
11.5 Supply clock ..................................................................................................................... 11-2
11.6 Register ............................................................................................................................ 11-3
11.6.1 SRAM/Flash mode register 0/2/4 (MCFMODE0/2/4) ................................................... 11-3
11.6.2 SRAM/Flash timing register 0/2/4 (MCFTIM0/2/4) ....................................................... 11-5
11.6.3 SRAM/Flash area register 0/2/4 (MCFAREA0/2/4) ...................................................... 11-8