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MB86R02 'Jade-D' Hardware Manual V1.64
30.6.2 SPI control register (SPInCR)
This register is to set common setting of SPI.
SPICR setting should be carried out in the sleep or setup states, and do not write to this register in
the busy state.
Each bit of SPICR is not cleared even the state is changed to sleep by SPE = 0 of SPI slave
control register (SPISCR.)
Address
Bit
31
30
29
Name
–
–
–
R/W
R0
R0
R0
Initial value
X
X
X
Bit
15
14
13
Name
–
–
–
R/W
R0
R0
R0
Initial value
X
X
X
(Note) This register should be accessed in 32 bit unit.
Bit field
No.
Name
31-19
–
18-17
–
16
SPL0
15-11
–
10-8
CDV2-0
7-2
–
1
CPOL
30-6
SPI0: FFF4_0000
SPI1: FFF4_5000
28
27
26
25
–
–
–
–
R0
R0
R0
R0
X
X
X
X
12
11
10
9
–
–
CDV2 CDV1 CDV0
R0
R0
R/W R/W R/W
X
X
0
0
Unused bits.
The write access is ignored. The read value of these bits is always "0".
Unused bits.
The write access is ignored.
Polarity of SPI_SS pin (slave selection pin) is specified.
0 Active-high (initial value)
1 Active-low
Unused bits.
The write access is ignored. The read value of these bits is always "0".
Frequency dividing ratio of serial clock (SCK) to bus clock (PCLK) is specified.
CDV2 CDV1 CDV0
PCLK × 1/2 (initial value)
0
0
0
PCLK × 1/4
0
1
0
PCLK × 1/8
0
1
0
PCLK × 1/16
0
1
1
PCLK × 1/32
0
0
1
PCLK × 1/64
0
1
1
PCLK × 1/128
1
0
1
PCLK × 1/256
1
1
1
Unused bits.
The write access is ignored. The read value of these bits is always "0".
Polarity of serial clock (SCK) is selected.
0 Positive pulse (initial value)
1 Negative pulse
+ 00
H
H
+ 00
H
H
24
23
22
21
–
–
–
–
R0
R0
R0
R0
X
X
X
X
8
7
6
5
–
–
–
R0
R0
R0
0
X
X
X
Description
Frequency dividing ratio
20
19
18
17
–
–
–
–
SPL0
R0
R0
R/W R/W R/W
X
X
0
0
4
3
2
1
–
–
–
CPOL CPHA
R0
R0
R0
R/W R/W
X
X
X
0
16
0
0
0
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