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MB86R02 'Jade-D' Hardware Manual V1.64
CUTC (Cursor Transparent Control)
Register
DisplayBaseAddress + 0xA0
address
Bit number
15
Bit field name
R/W
Initial value
Bit 7 to 0
CUTC (Cursor Transparent Code)
Sets color code handled as transparent code
Bit 8
CUZT (Cursor Zero Transparency)
Defines handling of color code 0
0
Code 0 as non-transparency color
1
Code 0 as transparency color
CPM (Cursor Priority Mode)
Register
DisplayBaseAddress + 0xA2
address
Bit number
7
Bit field name
Reserved
R/W
Initial value
This register controls the display priority of cursors. Cursor 0 is always preferred to cursor 1.
Bit 0
CUO0 (Cursor Overlap 0)
Sets display priority between cursor 0 and pixels of Console layer
0
Puts cursor 0 at lower than L0 layer.
1
Puts cursor 0 at higher than L0 layer.
Bit 1
CUO1 (Cursor Overlap 1)
Sets display priority between cursor 1 and C layer
0
Puts cursor 1 at lower than L0 layer.
1
Puts cursor 1 at lower than L0 layer.
Bit 4
CEN0 (Cursor Enable 0)
Sets enabling display of cursor 0
0
Disabled
1
Enabled
Bit 5
CEN1 (Cursor Enable 1)
Sets enabling display of cursor 1
0
Disabled
1
Enabled
18-96
14
13
12
11
10
Reserved
R0
0
6
5
CEN1
R0
RW
0
0
9
8
7
6
5
CUZT
RW
X
4
3
CEN0
Reserved
RW
R0
0
0
4
3
2
1
CUTC
RW
X
2
1
0
CUO1
CUO0
RW
RW
0
0
0
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