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MB86R02 'Jade-D' Hardware Manual V1.64
18.6.7 DCLKO shift
1) Delay
If the internal PLL is used to generate the DCLK, then it is possible to delay the DCLKO signal. The
DCKD field in the DCM3 register defines a delay value in units of internal PLL clock cycles.
DCKD (value in hex.)
0x00
0x02
0x04
0x06
0x08
0x0A
0x0C
0x0E
0x10
0x12
0x14
0x16
0x18
0x1A
0x1C
0x1E
2) Inversion
DCLKO inversion is also available with or without the delay functionality. This function is effective
without regard to the DCLK clock source.
The DCKinv bit of DCM3 enables this function.
18.6.8 Synchronous register updates and display
To update position related parameters without disturbing the display, it is necessary to update in synch
with the VSYNC interrupt and to complete this in time.
This synchronous register update mode eases this limitation. In this mode, written parameters are hold
in intermediate registers and update at once synchronously with VSYNC.
RUM-bit of DCM2 register enables this mode.
RUF-bit of DCM2 register controls start of update and shows whether update is done or not.
Delay
No delay (res)
+1 PLL clock
+2 PLL clocks
+3 PLL clocks
+4 PLL clocks
+5 PLL clocks
+6 PLL clocks
+7 PLL clocks
+8 PLL clocks
+9 PLL clocks
+10 PLL clocks
+11 PLL clocks
+12 PLL clocks
+13 PLL clocks
+14 PLL clocks
+15 PLL clocks
18-29
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