Video Capture Registers - Fujitsu MB86R02 Jade-D Hardware Manual

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MB86R02 'Jade-D' Hardware Manual V1.64
18.7.10

Video capture registers

VCM (Video Capture Mode)
Register address
Bit number
Bitfield name
RW
RW RW RX RW RW
Initial value
This register sets the video capture mode. This register is not initialized by software reset.
Bit1
Bit2
Bit20
Bit25-24
Bit28
Bit30
Bit31
-Procedure of video capture clock Stop-
1) 0 is written in bit31 (VIE) of the
2) 1 is written in bit28 (VICE) of the
-Procedure of video capture clock beginning-
1) 0 is written in bit28 (VICE) of the
CaptureBaseAddress + 0x00
31
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
CM Reserve VI
RW
0
0
X
0
X
00
VS (Video Select)
NTSC or PAL is selected for the code error detection. (only the RTB656 is input.)
0
NTSC
1
PAL
NRGB(Native RGB input on)
Native RGB mode is set up.
RGB video data is accepted via an internal RGB preprocessor which converts RGB to
0
YUV422
1
Native RGB
VI (Vertical Interpolation)
Sets whether to perform vertical interpolation
0
Performs vertical interpolation. The graphics are enlarged vertically by two times
1
Does not perform vertical interpolation
CM (Capture Mode)
Sets video capture mode. To capture vides, set these bits to "11".
00
Initial value
01
Reserved
10
Reserved
11
Capture
VICE (Video Input Clock Enable)
Capture clock enable
0
Enable
1
Disable
VIS(Video Input Select)
0
RBT656/601
1
RGB
VIE (Video Input Enable)
Enables video capture function
0
Does not capture video
1
Captures video
VCM
VCM
VCM
reserve
RX
RW
X
0
register and the video capture function is invalidated.
register and Stop does video capture clock.
register and video capture clock is made effective.
---
5 4 3
2
1
VS
RX
RW RW RX
X
0
0
18-121
0
X

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